Experience and Skills Needed: You should have five years of experience designing PLLs, frequency synthesizers, LO generation circuits, clock generation circuits, or clock and data recovery circuits, and your experience should include taking designs from concept through productization. You should have familiarity with wireless or wire-line communication specifications and derivation of block-level requirements from high-level specifications. You should have hands-on experience testing your own designs in the lab, and you must be able to define characterization and production test techniques for all building blocks, such as crystal oscillators, VCOs, and LO generation circuits. You must show a clear understanding of the architectural issues in integer-N and fractional-N PLLs, such as selection of loop bandwidth and tradeoffs required to meet phase noise, jitter, and spurious performance. You must be capable of leading frequency plan decisions from choice of reference frequency to LO generation. Communication and presentation skills are critical, and you should show a strong desire and potential to lead technology development.
Requirements:
Education/Training Needed: Minimum qualification: Master of Science or Ph.D. in Electrical Engineering.
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